The present invention relates to a semiconductor device, a method for manufacturing the semiconductor device, and a method for manufacturing a semiconductor memory device.
Interconnects and the like are formed on an interlayer insulating film formed on a semiconductor substrate. In order to achieve the high integration of the interconnects and the like along with the miniaturization of a semiconductor device, it is required to maintain the planarity of this interlayer insulating film.
In the planarization process of the interlayer insulating film by means of chemical-mechanical polishing (CMP), the polishing rate differs between a region where a gate pattern density is high and a region where the density is low. Consequently, this process has had the problem that a step arises in the upper surface of the polished interlayer insulating film.
In order to solve such a problem as described above, there has been proposed a method for further planarizing the interlayer insulating film by forming a dummy pattern in a region where a gate pattern density is low or no gate patterns are formed (for example, an element-isolating region) to uniformize the gate pattern density and reduce the difference in polishing rate (see, for example, Japanese Patent Laid-Open Nos. 2003-243617 and 2004-349622).
Now, an explanation will be made of an example of a method for manufacturing semiconductor device using such a method as described above. First, desired well and channel regions are formed in a semiconductor substrate. Then, a gate insulating film, a polysilicon film to serve as a gate electrode, and a first silicon nitride film to serve as a CMP stopper film are successively formed on the semiconductor substrate.
Then, a photoresist is formed in a desired region using a lithography technique. Using this photoresist as a mask, the first silicon nitride film, the polysilicon film, the gate insulating film and the semiconductor substrate are RIE (reactive ion etching)—processed to form a trench.
Subsequently, a first silicon dioxide film is deposited so as to fill the trench. Using the first silicon nitride film as a stopper, this first silicon dioxide film is planarized by means of CMP to form an element-isolating region (STI).
Subsequently, a photoresist is formed using a lithography technique, so as to shape into desired gate and dummy patterns. Then, RIE processing is performed using the photoresist as a mask.
At this time, the desired gate and dummy patterns having the gate insulating film, the polysilicon film and the first silicon nitride film are formed in an active area (element region separated by the element-isolating region). In addition, a dummy pattern composed of the first silicon dioxide film is formed in the element-isolating region.
Subsequently, impurity-diffused layers to serve as source and drain regions and gate sidewall films are formed. Then, a second silicon nitride film for covering the gate and dummy patterns and a BPSG (Boron Phosphorus Silicon Glass) film to serve as an interlayer insulating film are formed.
Subsequently, this BPSG film is planarized by means of CMP using the second silicon nitride film as a stopper. Then, a second silicon dioxide film is formed on the BPSG film to form a contact plug for contact with the impurity-diffused layer.
The gate and dummy patterns of the active area have the first silicon nitride film in a layer underlying the second silicon nitride film. On the other hand, the dummy pattern of the element-isolating region is such that a layer underlying the second silicon nitride film is the first silicon dioxide film. That is, the thickness of a silicon nitride film to serve as a stopper at the time of CMP is smaller in the element-isolating region than in the active area.
Accordingly, if the second silicon nitride film of the dummy pattern in the element-isolating region is entirely etched away when planarizing the BPSG film by CMP, the first silicon dioxide film underlying the second silicon nitride film is abraded. Consequently, the height of the dummy pattern in the element-isolating region becomes smaller than the heights of the gate and the dummy patterns in the active area, thus giving rise to a step therebetween. This step can be a cause for a short-circuit in an upper interconnect layer and for a yield decrease. In addition, this step may degrade an interlayer breakdown voltage.